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1/46 STLC5048 april 2005 1features fully programmable monolithic 4 channel codec/filter single +3.3v supply a/m law programmable linear coding (16 bits) option pcm highway format automatically detected:1.536 or 1.544 mhz2.048, 4.096, 8192 mhz two pcm ports available tx gain programming: 33db range; <0.01db step rx gain programming:42db range; <0.01db step programmable slic input impedance programmable transhybrid balance filter programmable equalization (frequency response) programmable time slot assignment digital and analog loopbacks slic control port static (16 i/os) dynamic (12 i/os + 4 cs) built-in test mode with tone generation, mcu access to pcm data 64 tqfp (10x10mm) package programmable slic line current limitation programmable slic off-hook detection threshold 2 description the STLC5048 is a monolithic fully programmable 4 channel codec and filter. it operates with a single +3.3v supply. the analog interface is based on a receive output buffer driving the slic rx input and on an amplifier input stage normally driven by the slic tx output. due to the single supply voltage a midsupply refer- ence level is generated internally by the device and all analog signals are referred to this level (agnd). the pcm interface uses one common 8khz frame sync. pulse for transmit and receive direction. the bit clock is automatically detected between four stan- dards: 1.563/1.544mhz, 2.048mhz, 4.096mhz, 8192mhz. two pcm port are provided: the channels can be connected to port a or/and b. device programmability is achieved by means of several registers and commands allowing to set the different parameters like tx/rx gains, line imped- ance, transhybrid balance, equalization (frequency response), encoding law (a/ ), time slot assignment, independent channels power up/down, loopbacks, pcm bits offset. the STLC5048 can be programmed via serial inter- face running up to 8 mhz. one interrupt output pin is also provided. a gui interface is also available to emulate and pro- gram the coefficients for impedance synthesis, echo cancelling and channel filtering. fully programmable four channel codec and filter fi gure 1. p ac k age table 1. order codes part number package STLC5048 tqfp64 STLC5048tr tqfp64 in tape & reel tqfp64 (10x10x1.4mm) rev. 8
STLC5048 2/46 figure 2. block diagram table 2. absolute maximum ratings table 3. operating range table 4. thermal data symbol parameter value unit v cc v cc to v ee 4.6 v v dd v dd to v ss 4.6 v vd in digital input pin voltage 5.5 v vain analog input pin voltage( v dd =v cc ; v ee =v sub )v cc + 0.5; v ee - 0.5 v t stg storage temperature range -65 to +150 c t lead lead temperature (soldering, 10s) 300 c symbol parameter value unit v cc , v dd supply voltage 3.3 +/- 5% v t op operating temperature range -40 to +85 c symbol parameter value unit r th j-amb thermal resistance junction-ambient 70 c/w d/a ch0 pll block analog front end vcc vee vdd vss sub cap m1 m0 digital processor 8 bias gener. slic thr ith ilim vbg d00tl467 decoder controller to analog fe interpolat. decimators kd filters slic interface config. registers serial interface shappire macro control interface coeff bus data interface a/u law gr0 gx0 a/d ch0 d/a ch1 gr1 gx1 a/d ch1 encoder pcm interface fs vfro0 vfx10 vfro1 vfx11 vfro2 vfx12 vfro3 vfx13 mclk dra drb dxa dxb tsxa tsxb io11 io10 io9 io8 io7 io6 io5 io4 io3 io2 io1 io0 cs3 cs2 cs1 cs0 int cclk ci co cs a/u law d/a ch2 gr2 gx2 a/d ch2 d/a ch3 gr3 gx3 a/d ch3 8 16 16
3/46 STLC5048 figure 3. pin connection (top view) 3 pin description 3.1 i/o definition type definition ai analog input ao analog output odo open drain output di digital input do digital output dio digital input / output dto digital tristate output dps digital power supply aps analog power supply 1 2 3 5 6 4 7 8 9 10 27 11 28 29 30 31 32 59 58 57 56 54 55 53 52 51 50 49 43 42 41 39 38 40 48 47 46 44 45 ci co cs n.c. n.c. int dxa dra vdd cclk vss io3 io4 io5 vcc5 m0 vee5 cs0_ cs1_ vee1 vee0 res io9 io10 io11 vcc4 m1 vee4 cs2_ cs3_ vee2 vee3 vbg vfxi2 vfro2 sub vfro1 vfxi1 cap vfro3 ilim vfxi3 vcc2 vcc3 d94tl150 22 23 24 25 26 60 io8 61 io7 62 io6 63 n.c. 64 res. tsxb_ n.c. io0 io1 io2 17 18 19 20 21 37 36 34 33 35 vcc1 vcc0 ith vfro0 vfxi0 12 13 14 15 16 drb dxb fs tsxa mclk
STLC5048 4/46 3.2 analog pin description 3.3 not connected 3.4 power supply pin description no. name type description 33 vfro0 ao receive analog amplifier output channel 0. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 39 vfro1 ao receive analog amplifier output channel 1. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 42 vfro2 ao receive analog amplifier output channel 2. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 48 vfro3 ao receive analog amplifier output channel 3. pcm data received on the programmed time slot on dr input is decoded and appears at this output. 35 vfxi0 ai tx input amplifier channel 0. typ 1m ? input impedance 38 vfxi1 ai tx input amplifier channel 1. typ 1m ? input impedance 43 vfxi2 ai tx input amplifier channel 2. typ 1m ? input impedance 46 vfxi3 ai tx input amplifier channel 3. typ 1m ? input impedance 40 cap agnd voltage filter pin: a 100nf capacitor must be connected between ground and this pin. 34 ith ao slic off hook detection threshold. 47 ilim ao slic line current limitation. 49 vbg ai slic vbg reference for dc characterisrics programmability. 2, 18, 63, 1 n.c. not connected, must be left open 32, 64 res reserved pins, must be connected to ground 25,36, 37,44, 45,56 vcc0..5 aps total 6 pins: 3.3v analog power supplies, should be shorted together, require 100nf decoupling capacitor to vee. 26,30, 31,50, 51,55 vee0..5 aps total 6 pins: analog gr ound, should be shorted together. 9 vdd dps digital power supply 3.3v, require 100nf decoupling capacitor to vss. 8 vss dps digital ground. 41 sub dps substrate connection. must be shorted together with vee and vss pins.
5/46 STLC5048 3.5 digital pin description no. name type description 27 54 m0 m1 di mode select. m1 m0 mode select 0 0 reset status 1 0 normal operation 0 1 not allowed 1 1 not allowed 14 fs di frame sync. pulse. a pulse or a square waveform with an 8khz repetition rate is applied to this pin to define the start of the receive and transmit frame. effective start of the frame can be then shifted of up to 7 clock pulses independently in receive and transmit directions by proper programming of the pcmsh register. 13 mclk di master clock input. four possible frequencies can be used: 1.536/1.544 mhz; 2.048 mhz; 4.096 mhz; 8.192 mhz. the device automatically detect the frequency applied. this signal is also used as bit clock and it is used to shift data into and out of the dra/b and dxa/b pins. 12 tsxa odo transmit time slot (open drain output, 3.2ma). normally it is floating in high impedance state except when a time slot is active on the dxa output. in this case tsxa output pulls low to enable the backplane line driver. 11 dxa dto transmit pcm interface a. it remains in high impedance state except during the assigned time slots during which the pcm data byte is shifted out on the rising edge of mclk. 10 dra di receive pcm interface a. it remains inactive except during the assigned receive time slots during which the pcm data byte is shifted in on the falling edge of mclk. 24 io5 dio general control i/o pin #5. can be programmed as input or output via dir register. depending on content of conf register can be a static input/output or a dynamic input/output synchronised with the csn output signals controlling the slics. 62 io6 dio general control i/o pin #6. (see io5 description). 61 io7 dio general control i/o pin #7. (see io5 description). 60 io8 dio general control i/o pin #8. (see io5 description). 59 io9 dio general control i/o pin #9. (see io5 description). 58 io10 dio general control i/o pin #10. (see io5 description). 57 io11 dio general control i/o pin #11. (see io5 description). 19 io0 dio general control i/o pin #0. (see io5 description). 20 io1 dio general control i/o pin #1. (see io5 description). 21 io2 dio general control i/o pin #2. (see io5 description). 22 io3 dio general control i/o pin #3. (see io5 description). 23 io4 dio general control i/o pin #4. (see io5 description).
STLC5048 6/46 no. name type description 28 cs0 dio slic cs control #0. depending on conf reg. content can be a cs output for slic #0 or a static i/o. when configured as cs output it is automatically generated by the codec with a repetition time of 31.25ms. in this mode also the io0..11 are synchronised and carry proper data in and out synchronous with cs. when configured as static i/o, the direction is defined by csdir register content. 29 cs1 dio slic cs control #1, (see cs0 description). 53 cs2 dio slic cs control #2, (see cs0 description). 52 cs3 dio slic cs control #3, (see cs0 description). 4 cs di chip select input, when this pin is low control information can be written to or read from the device via the ci and co pins. 7 cclk di clock of serial control bus. this clock shifts serial control information into or out of ci or co when cs input is low depending on the current instruction. cclk may be asynchronous with the other system clocks. 6 ci di control data input of serial control bus. control data is shifted in the device when cs is low and clocked by cclk. depending on the addressed register different numbers of consecutive bytes can be loaded. 5 co di control data output of serial control bus. control data is shifted out the device when cs is low and clocked by cclk. depending on the addressed register different numbers of consecutive bytes can be shifted out. 3 int odo interrupt output (open drain), goes low when a data change has been detected in the i/o pins or another interrupt source is active. one mask register allows to mask any i/o pin. interrupt is reset when the i/ o register is read. 17 tsxb odo transmit time slot (open drain output, 3.2ma). normally it is floating in high impedance state except when a time slot is active on the dxb output. in this case tsxb output pulls low to enable the backplane line driver. 15 dxb dto transmit pcm interface b. it remains in high impedance state except during the assigned time slots during which the pcm data byte is shifted out on the rising edge of mclk. 16 drb di receive pcm interface b. it remains inactive except during the assigned receive time slots during which the pcm data byte is shifted in on the falling edge of mclk. 3.4 digital pin description (continued
7/46 STLC5048 4 functional description the STLC5048 is a fully programmable device with embedded rom and ram. the rom is used to contain the default state coefficients for the programmable filters, while the ram is used to load the desired coefficient values. 4.1 power on initialization when power is first applied it is recommended to reset the device (m1=m0=0) in order to set all the internal reg- isters to the reset value (see register description); this means also power down mode for all the four channels and sw reset bit (res) set in the conf register. when the res bit is set, the only instructions allowed are the one that disable this bit and the reacom instruc- tion: all other instructions are ignored. it is not possible to disable the res bit and write the other bits of the conf register with the same instruction. of course, reset mode can be programmed also by writing the res bit of the conf register. see appendix c for the power up sequence. during reset condition all the i/on and csn pins are set as inputs, dx is in high impedance and all vfron are set to agnd. after the reset all registers are loaded with the reset value. it means that the pcm interface and all the vfro outputs are configured as described in the power down state, while no transmit or receive time slot are set. then, filters and gain blocks are configured with the coefficient defined in the default state. 4.2 power down state each of the four channel may be put into power down mode by setting the appropriate bit in the conf register. in this mode the eventual programmed dx channel is set in high impedance while the vfro outputs are forced to agnd. when all the channels are set in power down mode the device enters the power down state: all the blocks related to the data processing are turned off, while the ram is on or off according to the pdr bit value in the comen register. figure 4. block diagram of a single channel. a/mu dr vfro vfxi hpr r gr b z kd ka ** * * *** * lpr d/a rx tx a/mu dx hpx x gx ** * programmable blocks d00tl468 lpx a/d
STLC5048 8/46 4.3 ringing state this state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 hz). in order to obtain a 1 vrms ringing signal at vfro output a digital signal dr equal to -0.78dbm0 must be pro- vided. this state means b, z, x, kd and ka blocks equal to open circuits and the r block configured in order to obtain the maximum gain at the frequency of 25-50 hz. during the ringing state if the tx time slot is enabled the idle pcm code is forced to dx. to switch to this state, a bit (fr0..3) in the coefst register must be set for every channel. the programmed values for the previous blocks become active only when the fr and fd bits are reset. if both fr and fd bits of a channel are set, the selected coefficient will be those of the ringing state. 4.4 impedance synthesys the impedance synthesis is performed by fully digital filters (z and kd) and by an analog path (ka). the z, kd and ka filters report to the receive path the feedback signal coming from the transmit path. the co- efficients of the z, kd and ka filters are programmed via the zfc, kd and afe_cff commands respectively. 4.5 echo canceling the trans-hybrid balance is performed by the digital programmable filter b. the b filter reports to the transmit path the signal coming from the receive path. the coefficient of the b filter are programmed via the bfc command. figure 5. transmit path. 4.6 transmit path the transmit section input consist of the input amplifier, the a/d converter, the equalization filter x, the gain block gx, the encoder and the channel filters (lpx and hpx). the input amplifier is provided of a programmable gain with a typical input impedance of 1m ? . the amplifier gain can be programmed with two different values (0db, +3.52db) by means of the txg register. vfxi input must be ac coupled to the signal; the voltage swing allowed is 1.4vpp when the preamplifier gain is set to 0db and 0.93vpp when the gain is 3.52db; higher levels must be reduced through proper dividers. following the input amplifier the signal is converted into digital domain and a x filter block is programmed to equalise together with the hpx and lpx filters the frequency response. the coefficients of the x filter are pro- grammed via the xfc command. a gain block (gx) allows to set the transmit level in a 30db range, with steps <0.01db. this block can be pro- grammed via the gtx command. the needed tx gain can be set by proper programming of the gx block in combination with the tx amplifier. setting gtx=00h, the transmitted signal is muted and an idle pcm signal is generated on dx. dx txg vfxi 1m ? agnd ? conv. gxo a/ gx for txg=0db; gx=0db (ff) 61mvms => 0dbm0 d00tl469
9/46 STLC5048 concerning the coding function, a/m law can be selected writing the conf register (bit 5 amu). in addition, via the conf register (bit 6 lin) the coding law can be set to linear mode (16 bits). in this case the signal sent on the dx will take two adjacent pcm channels, proper care has to be taken in the time slot selection program- ming (dxts register). the intrinsec non programmable gain gx0 set the tx path gain to 22.07db. the absolute gain level (see elec- trical characteristics) refers to this intrinsec gain. 4.7 receive path the receive path of the STLC5048 consists of the decoder section, the gain block gr, the r filter, the channel filters (lpr, hpr) the d/a converter and the output amplifier. concerning the decoding function, a/m law can be selected writing the conf register (bit 5 amu). in addition via the conf register (bit 6 lin) the coding law can be set to linear mode (16 bits). in this case the signal received on the dr input will take two adjacent pcm channels, proper care has to be taken in the time slot selection programming (drts register). the gain block gr is controlled by the grx command allowing 30db gain range in 0.01db steps. the r filter together the channel filters (lpr and hpr) performs the line equalization. the coefficients of the r filter are programmed via the rfc command. the signal is converted in the analog domain and amplified by the rx amplifier that can be programmed with four different values (mute, 0db, -6db and -12db) by means of rxg register. figure 6. receive path. vfro output, referred to agnd must be ac coupled to the load, referred to vss, to prevent a dc current flow. in order to get the best noise performances it is recommended to keep grx value as close as possible to the maximum (ffh) setting properly the additional attenuation by means of rxg. the intrinsec non programmable gain gr0 set the rx path gain to -3.15db. the absolute gain level (see elec- trical characteristics) refers to this intrinsec gain. 4.8 pcm interface the STLC5048 dedicates eight pins to the interface with the pcm highways. mclk represents the bit clock and is also used by the device as a source for the clock of the internal pll. five possible frequencies can be used: 1.536/1.544mhz (24 channels pcm frame); 2048mhz (32 channels pcm frame); 4.096mhz (64 channels pcm frame); 8.192mhz (128 channels pcm frame). the operating fre- quency is automatically detected by the device the first time both mclk and fs are applied and becomes active after the second fs period. mclk synchronises both the transmit data (dxa/b) and the receive data (dra/b). the frame sync. signal fs is the common time base for all the four channels. dr rxg vfro ? conv. gro a/ gr for rxg=0db; gr=0db 0dbm0 => -3dbm/ 600 ? d00tl470
STLC5048 10/46 transmit and receive programmable time-slots are framed by an internal sync. signal that can be coincident with fs or delayed of 1 or 7 mclk cycles depending on the programming of pcmsh register. two pcm ports are available: every channel can be connected to a different pcm port by means of pcmcom register. dxa/b represents the transmit pcm interface. it remains in high impedance state except during the assigned time slots during which the pcm data byte is shifted out on the rising/falling edge of mclk according to the te bit of pcmcom register. the four channels can be shifted out in any possible timeslot as defined by the dxts registers. the assigned time slot (transmit and receive) takes place in the 8 mclk cycles following the rising edge of fs. the data can be shifted out on port a and/or b according to pcmcom register. if one codec is set in power down by software programming the corresponding time slot is set in high imped- ance. when linear coding mode is selected by conf register programming the output channel will need two consecutive time slots (see register description). dra/b represents the receive pcm interface. it remains inactive except during the assigned time slots during which the pcm data byte is shifted in on the falling edge of mclk. the four channels are shifted in any possible time slot as defined by the drts registers. if one codec is set in power down by software programming the corresponding time slot is not loaded and the vfro output is kept at steady agnd level. table 5. instruction byte structure r/w =0: write operation r/w =1: read operation i6..i0: instruction identifier: it can be a register address or a command identifier. the number of data bytes depends on the instruction type. the first bit of a byte is the msb, the first byte of an instruction is the lsbyte. when linear coding mode is selected by conf register programming the input channel will need two consecu- tive time slots (see register description). the data can be shifted in from port a or b according to the pcmcom register. tsxa/b represents the transmit time slot (open drain output, 3.2ma). normally it is floating in high impedance state except when a time slot is active on the dxa/b output. in this case tsxa/b output pulls low to enable the backplane line driver. should be strapped to vss when not used. finally by means of the loopb register it is possible to implement a digital or analog loopback on any of the selected channels. 4.9 mcu control interface the mcu serial control interface consists of 4 pins. cclk: control clock ci: serial data in co: serial data out cs: chip select input control instructions require at least two bytes: however two single byte instructions are also provided. in the multiple byte instructions the first one specifies the command or the register address and the access type (read or write). the following bytes contain the data to be loaded into the internal ram (on ci wire) or carry out the ram content (on co wire) depending on the r/w bit of the first byte. co wire is normally in high impedance and goes to low impedance only after the first byte in case of read operation. this allows to use a common wire for both ci/co. first byte (address or command id) following bytes (data) 7654321076543210 r/wi6 i5 i4 i3 i2 i1 i0 d7d6d5d4d3d2d1d0
11/46 STLC5048 cs, normally high, is set low during the transmission/reception of a byte, lasting 8 cclk pulses. between two consecutive access the cs must be set high. the cclk can be a continuos or a gated clock. the result of any instruction (read/write operation), if negative, can generate an interrupt (maskable). the inter- rupt register (int) contains the cause information of the generated interrupt and it is cleared every time that it is read. depending on the instruction specified in the first byte, the STLC5048 waits a defined number of data bytes. if the STLC5048 doesn't receive the data byte within a predefined period specified by means of t_out command, an internal time out rejects the instruction. the time-out time is verified between two consecutive mcu interface access (between the falling edge of the cs and the following rising edge). this feature is used to verify the synchronisation of the mcu interface: however it can be disabled if not desired (see t_out reg description). to check this synchronisation is provided a specific register (synck) that returns always a predefined value: if the returned value is different the mcu interface is in out of sync state (the device is waiting a data byte while the mcu is writing an address or vice versa). in this case, it is possible to realign it by means of the execution of a specific single byte instruction (reacom) from 1 to 53 times, depending on the instructions. every time an illegal operation (access to not allowed address, time-out violation or clock pulse different than 8 inside a cs active) is performed the mcu interface is put on an error state: to resume it from this state a single reacom instruction can be used. anyway after a reacom instruction a successful sync instruction guarantees the correct synchronisation. one additional wire provided to the control interface is an open drain interrupt output (int) that goes low when a change of status is detected on the i/o pins or other interrupt source are active (see int register). int is au- tomatically reset after reading of the register corresponding the cause that has generated the interrupt (see int register description). a particular register (comen) allows to enable a command on different channel at the same time. every time a command operation is performed at least one channel must be enabled in this register. this feature is useful when all channels must be configured in the same condition. when a command is used to perform a read operation only one channel can be enabled at the same time. to check the configuration of the device a checksum value is provided. this value is calculated on all coefficient parameters entered (coefficients of kd, afe_cff, grx, gtx, rfc, xfc, bfc, zfc blocks; see cksum reg- ister description). two commands are required to get this value: the first one (ckstart) starts the internal checksum calculation, the second one (cksum) returns the calculated value. between this two commands no other operation are allowed. the checksum value is available within 400us the ckstart command. coefficient checksum is defined by this algorithm: x 16 + x 12 + x 5 + 1 this algorithm guarantees a fault coverage of 1 - 2 -16 . 4.10 programming the device after the power up, the filters and gain blocks can be programmed also with all the channels set in power down. in this case the pdr bit of the comen register must be set to 0. with the proper setting of the comen register, the commands can be applied to more than one channel at the same time. to read the coefficient values loaded in the ram, only one channel per time must be enabled in the comen register.
STLC5048 12/46 4.11 slic control interface the device provides 12 i/o pins plus 4 cs signals. the interface can work in dynamic or static mode: it can be selected by means of sta bit of the conf register. dynamic mode: the i/o pins are configured as input or output by means of dir register. the cs signals are used to select the different slic interface. in this case the i/o pin can be multiplexed. the data loaded from slic #n via i/o pins configured as input can be read in the datan register. the data written in a datan register will be loaded on the i/o pins configured as output when the csn signal will be active. static mode: the cs signal can be used as i/o pins. they can be configured as input or output i/o by means of data1 register. the data corresponding to the cs signal can be read or written by means of data2 register. all data related to the other i/o pins can be read or written by means of data0 register. 4.12 dc slic programmability three additional pins are used to select the on-hook/off-hook detection threshold and the line card limitation of the stlc3080 slic. this two values are programmed by ilim and ith registers. the programmation of these two registers must be done before the filter coefficients download. the vbg input pin must be connected to the iref pin of the stlc3080. when the l3235n is used in kit with STLC5048 the ilim, ith and vbg pin must be not connected. 4.13 built in test by means of toneg register it is possible to inject a tone of variable frequency (25hz, 1 and 3khz) and 0dbm0 amplitude into the receive path, replacing any signal coming from the pcm interface. this test can be performed on every channel. setting the proper bit of the pcmcom register is also possible to read/write the pcm data coming from the transmit path via the mcu interface (pcmrd/pcmwd registers). this feature can be enabled only on one channel per time. these two features can be used to test the line interface operation. table 6. register addresses addr name description 00h dir-l i/o direction (bit 7-0) 01h dir-h i/o direction (bit 11-8) 02h data0-l i/o data ch#0 (bit 7-0) 03h data0-h i/o data ch #0 (bit 11-8) 04h data1-l i/o data ch#1 (bit 7-0) 05h data1-h i/o data ch #1 (bit 11-8) 06h data2-l i/o data ch#2 (bit 7-0) 07h data2-h i/o data ch #2 (bit 11-8) 08h data3-l i/o data ch#3 (bit 7-0) 09h data3-h i/o data ch #3 (bit 11-8) 0ah pchk-a persistency check time for input a 0bh pchk-b persistency check time for input b 10h int interrupt register 11h dmask-l int. mask i/o port (03h)
13/46 STLC5048 addr name description 12h dmask-h int. mask i/o port (04h) 13h imask interrupt mask reg. 14h alarm alarm register 20h conf configuration register 21h comen command enable reg. 23h syncck synchronous check reg. 25h ctrlack dsp status register 26h cksum-l cheksum register l 27h cksum-h cheksum register h 2ah loopb loopback register 2bh txg transmit preamp. gain 2ch rxg receive preamp. gain 2dh ilim slic line current lim. 2eh ith slic off-hook threshold 50h pcmsh pcm shift register 51h pcmcom pcmcom register 52h dxts0 transmit timeslot ch #0 53h dxts1 transmit timeslot ch #1 54h dxts2 transmit timeslot ch #2 55h dxts3 transmit timeslot ch #3 56h drts0 receive timeslot ch #0 57h drts1 receive timeslot ch #1 58h drts2 receive timeslot ch #2 59h drts3 receive timeslot ch #3 5ah pcmwd-l pcmw data register 5bh pcmwd-h pcmw data register 5ch pcmrd-l pcmr data register 5dh pcmrd-h pcmr data register 5eh pcmctrl pcm control register 60h toneg tone generation reg. 61h coefst coefficient state reg. 70h swrid software rev. id code 71h hwrid silicon revision id code table 6. register addresses (continued)
STLC5048 14/46 5 register description 5.1 i/o direction register (dir) addr=00h; reset value=00h addr=01h; reset value=x0h io11..0=0 i/o pin 11..0 is an input, data on the i/o input is written in datan register bit 11..0. io11..0=1 i/o pin 11..0 is an output, data contained in datan register bit 11..0 is transferred to the i/o output. 5.2 i/o data register channel #0 (data0) addr=02h; reset value=00h addr=03h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: when cs0 is active d011..0 are transferred to the corresponding i/o pins configured as outputs (see dir reg- ister). for the i/o pins configured as inputs the corresponding d011..0 will be written by the values applied to those pins while cs0 is low. if bit 4 of conf register (sta)=1 static i/o mode: ds11..0 are transferred to the corresponding i/o pins configured as outputs (see dir register). for the i/o pins configured as inputs the corresponding ds11..0 will be written by the values applied to those pins. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000000 io 7 io 6 io 5 io 4 io 3 io 2 io 1 io 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000001 io 11 io 10 0io 9 io 8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000010 d0 7 d0 6 d0 5 d0 4 d0 3 d0 2 d0 1 d0 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000011 d0 11 d0 10 d0 9 d0 8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000010 ds 7 ds 6 ds 5 ds 4 ds 3 ds 2 ds 1 ds 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000011 ds 11 ds 10 ds 9 ds 8
15/46 STLC5048 5.3 i/o data register channel #1 (data1) addr=04h; reset value=00h addr=05h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: when cs1 is active d111..0 are transferred to the corresponding i/o pins configured as outputs (see dir reg- ister). for the i/o pins configured as inputs the corresponding d111..0 will be written by the values applied to those pins while cs1 is low. if bit 4 of conf register (sta)=1 static i/o mode: in static mode cs pins are used as additional i/o pins. the cio0..3 bits are used to define the direction of these pins. cio0..3=0 the cs0..3 is a static input, data is written in data2 register bits 0..3. cio0..3=1 the cs0..3 is a static output, data is taken from data2 register bits 0..3. 5.4 i/o data register channel #2 (data2) addr=06h; reset value=00h addr=07h; reset value=x0h if bit 4 of conf register (sta)=0 dynamic i/o mode: when cs2 is active d211..0 are transferred to the corresponding i/o pins configured as outputs (see dir reg- ister). for the i/o pins configured as inputs the corresponding d211..0 will be written by the values applied to those pins while cs2 is low. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000100 d1 7 d1 6 d1 5 d1 4 d1 3 d1 2 d1 1 d1 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000101 d1 11 d1 10 d1 9 d1 8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000100 cio 3 cio 2 cio 1 cio 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000110 d2 7 d2 6 d2 5 d2 4 d2 3 d2 2 d2 1 d2 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w000011 1 d2 11 d2 10 d2 9 d2 8
STLC5048 16/46 if bit 4 of conf register (sta)=1 static i/o mode: cd0..3 are transferred to the corresponding cs pin if configured as static output (see register data1). for the cs pins configured as static inputs the corresponding cd0..3 will be written by the values applied to those pins. 5.5 i/o data register channel #3 (data3) addr=08h; reset value=00h addr=09h; reset value=x0h used only if bit 4 of conf register (sta)=0; dynamic i/o mode: when cs3 is active d311..0 are transferred to the corresponding i/o pins configured as outputs (see dir reg- ister). for the i/o pins configured as inputs the corresponding d311..0 will be written by the values applied to those pins while cs3 is low. if bit4 of conf register (sta) = 1 static i/o mode: d3 3..0 =1: the corresponding csn cannot generate interrupt. d3 3..0 =0: the corresponding i/o (programmed as input) can generate interrupt if a change of status is detected. 5.6 persistency check register (pchk-a/b) addr=0ah; reset value=00h addr=0bh; reset value=00h two input signal per channel, labelled a and b, are submitted to persistency check. in dynamic mode (sta=0), a and b inputs of the four channels, are sampled on the multiplexed lines io0 (pin 13) and io1 (pin 14). in static mode (sta=1) persistency check is performed on four pairs of lines, assigned to each channel accord- ing to the table: bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0000110 cd 3 cd 2 cd 1 cd 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0001000 d3 7 d3 6 d3 5 d3 4 d3 3 d3 2 d3 1 d3 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0001001 d3 11 d3 10 d3 9 d3 8 chan # input a input b 0io 0 (pin 19) io 1 (pin 14) 1io 4 (pin 17) io 5 (pin 18) 2io 6 (pin 48) io 7 (pin 47) 3io 10 (pin 44) io 11 (pin 43)
17/46 STLC5048 ta7..0 and tb7..0, contents of pchka and pchkb registers, define the minimum duration of input a and b to generate interrupt; spurious transitions shorter than the programmed value are ignored. the time width can be calculated according to the formula: time - width a = (ta7..0)*64 s time - width b = (tb7..0)*64 s if pchka/b is programmed to 00h the persistency check is not performed and any detected transition will gen- erate interrupt. all the inputs, with or without persistency check, are sampled with a repetition rate of 32 s. 5.7 interrupt register (int) addr=10h; reset value=00h read only in dynamic i/o configuration the id3..0 bits latch the interrupt request from the related channel (slic). any sin- gle bit idn is cleared after reading related i/o register or by setting mcn bit high (i.e. when channel n is disabled to generate interrupt). in static i/o configuration id0 and id2 bits latch the interrupt request from i/o11..0 and cs3..0 respectively: id0: is set high when the interrupt is requested from any the i/o11..0 lines. id2: is set high when the interrupt is requested from any the cs3..0 (configured as i/o). id0 and id2 are cleared after reading related i/o register. id1 and id3 are don?t care. itv = 1: if the interrupt has been generated by time-out violation on the mcu serial interface. ipcm = 1: when transmit pcm data reading/writing test is enabled an interrupt is generated every time valid data are available (rrd bit set to 1) or must be written (wrd bit set to 1). the interrupt is cleared after reading/ writing the data in the pcmrd/pcmwd register via the mcu interface. ickf = 1: if the interrupt has been generated by a clock failure on pcm port (mclk). the int register is cleared after reading operation only if signals (alarm cause) are inactive. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0001010 ta 7 ta 6 ta 5 ta 4 ta 3 ta 2 ta 1 ta 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0001011 tb7 tb6 tb5 tb4 tb3 tb2 tb1 tb0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10010000 itv ipcm ickf id3 id2 id1 id0
STLC5048 18/46 5.8 interrupt mask register for i/o port (dmask) addr=11h; reset value=ffh addr=12h; reset value=xfh md 11..0 =1: the corresponding i/o doesn?t generate interrupt. md 11..0 =0: the corresponding i/o (programmed as input) generate interrupt if a change of status is detected. input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register pchka/b. line without persistency check generate an immedi- ate interrupt request. mask register has no effect on those pins configured as outputs, those pins will not generate interrupt. 5.9 interrupt mask register for interrupt (imask) addr=13h; reset value=ffh for dynamic i/o configuration, mcn bits are the disable/enable interrupt related to the channel n. mc3..0=1: any i/o line of the related channel #n is disabled to generate interrupt independently of dmask setting. mc3..0=0: any i/o line of the related channel #n is enabled to generate interrupt depending on dmask setting. for static i/o configuration, mcn bits are the interrupt mask bits related to csn that are configured as i/o lines. mc0=1: the corresponding i/o cannot generate interrupt independently of dmask setting. mc0=0: the corresponding i/o can generate interrupt if a change of status is detected depending of dmask setting. mc2=1: the corresponding i/o cannot generate interrupt independently of data3_l setting (bit 3..0). mc2=0: the corresponding i/o can generate interrupt if a change of status is detected depending of data3_l setting (bit 3..0). mc3 and mc1 bit are not used in static mode. input lines with persistency check generate interrupt if the changed status remains stable longer than the time programmed in the persistency check register pchka/b. line without persistency check generate an immedi- ate interrupt request. mask register has no effect on those pins configured as outputs, those pins will not generate interrupt mcf=1: the corresponding alarm bit (ckf) doesn?t generate interrupt. mcf=0: the corresponding alarm bit (ckf) can generate interrupt. mtv=1: the corresponding alarm bit (tv) doesn?t generate interrupt. mtv=0: the corresponding alarm bit (tv) can generate interrupt. mpcm =1 : the ipcm interrupt is masked (generation disabled). mpcm =0 : the ipcm interrupt is enabled (generation enabled). bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0010001 md 7 md 6 md 5 md 4 md 3 md 2 md 1 md 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0010010 md 11 md 10 md 9 md 8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0010011 x mtv mpcm mcf mc3 mc2 mc1 mc0
19/46 STLC5048 5.10 alarm register (alarm) addr=14h; reset value=01h read only por=0: no power on reset is detected during operation. por=1: a power on reset is detected during operation. the alarm register is cleared after reading operation only if signals (alarm cause) are inactive. 5.11 configuration register (conf) addr=20h; reset value=bfh res=0 normal operation res=1 device reset: i/0n and csn are all inputs, dx is h.i. (equivalent to hw reset). lin=0 a or law pcm encoding lin=1 linear encoding (16 bits), two?s complement. amu=0 law selection (all bits inverted) amu=1 a law selection (even bits inverted) sta=0 cs0 to cs3 scan the four slics connected to the i/o control port, each cs has a 31.25 s repetition time. sta=1i/o are static, cs0 to cs3 are configured as generic static i/o pd3..0=0 codec 3..0 is active pd3..0=1 codec 3..0 is in power down. when one codec is in power down the corresponding vfro output is set to agnd and the corresponding transmit time slot on dx is set in h.i. 5.12 command enable register (comen) addr=21h; reset value=80h the en bits enable a command on one or more channels. all enabled channels will receive the entered data. at least one channel must be enabled before every command. e0..3=0: commands disabled on the corresponding channel 0..3 e0..3=1: commands enabled on the corresponding channel 0..3 pdr = 0: ram is enabled also in power down. pdr = 1: ram is disabled in power down. in this way it?s possible to reduce the power consumption in power down. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10010100 0000000por bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0100000 res lin amu sta pd3 pd2 pd1 pd0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0100001 pdr000e 3 e 2 e 1 e 0
STLC5048 20/46 5.13 synchronous check register (synck) addr=23h; reset value=e4h read only this register contains a fixed code (e4h) that can be read to check the synchronisation of the mcu interface. 5.14 dsp status register (ctrlack) addr=25h; reset value=01h read only ckend bit is 0 while the checksum calculation is performed: in the other time is always set to 1. init bit becomes active (init = 1) after the dsp initialization. normally it requires 70 us after the reset to be set to 1. 5.15 checksum register (cksum) addr=26h; reset value=00h addr=27h; reset value=00h read only the cheksum value is calculated every time the ckstart instruction is performed and the result is available after a proper delay (max 400 s). this register contains the cheksum value calculated on the contents of the following coefficient (each of 16 bits): zero kdf0_0 kdf0_1 kdf0_2 kdf1_0 kdf1_1 kdf1_2 kdf2_0 kdf2_1 kdf2_2 kdf3_0 kdf3_1 kdf3_2 afe_cff grx0 gtx0 rfc0_0 ...... rfc0_16 xfc0_0 ...... xfc0_16 bfc0_0 ...... bfc0_25 zfc0_0 ...... zfc0_4 grx1 gtx1 rfc1_0 ...... rfc1_16 xfc1_0 ...... xfc1_16 bfc1_0 ......bfc1_25 zfc1_0 ...... zfc1_4 grx2 gtx2 rfc2_0 ......rfc2_16 xfc2_0 ...... xfc2_16 bfc2_0 ...... bfc2_25 zfc2_0 ...... zfc2_4 grx3 gtx3 rfc3_0 ...... rfc3_16 xfc3_0 ...... xfc3_16 bfc3_0 ...... bfc3_25 zfc3_0 ......zfc3_4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100011 11100100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1010010 1 000000initckend bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100110 ck 7 ck 6 ck 5 ck 4 ck 3 ck 2 ck 1 ck 0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 10100111 ck 15 ck 14 ck 13 ck 12 ck 11 ck 10 ck 9 ck 8
21/46 STLC5048 5.16 loopback register (loopb) addr=2ah; reset value=00h dl3..0=0: normal operation dl3..0=1: codec #3..0 is set in digital loopback mode, this means that the receive pcm signal applied to the programmed receive time slot is transferred to the programmed transmit time slot. al3..0=0: normal operation al3..0=1: codec #3..0 is set in analog loopback mode, this means that the vfro signal is transferred to the vfxi input internally into the codec. when loopbacks are enabled the signal appears also at the corresponding vfro output. it is possible to have no signal on the vfro output programming the grx command to 00h in case of digital loopback. 5.17 transmit preamplifier gain register (txg) addr=2bh; reset value=00h tg3..0=0: transmit preamplifier gain ch. 3..0 = 0db tg3..0=1: transmit preamplifier gain ch. 3..0 = 3.52db overall transmit gain depends on combination of txg and gtxn registers. 5.18 receive amplifier gain register (rxg) addr=2ch; reset value=00h rn 0 =0,rn 1 =0: receive amp. gain ch #n = mute rn 0 =1,rn 1 =0: receive amp. gain ch #n = -12db rn 0 =0,rn 1 =1: receive amp. gain ch #n = -6db rn 0 =1,rn 1 =1: receive amp. gain ch #n = 0db overall receive gain depends on the receive amplifier gain (r3..0) setting in rxg reg. and digital gain (grxn reg. setting). bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1011010 dl3 dl2 dl1 dl0 al3 al2 al11 al0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0101011 tg3tg2tg1tg0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0101100 r3 1 r3 0 r2 1 r2 0 r1 1 r1 0 r0 1 r0 0
STLC5048 22/46 5.19 slic line current limit reg (ilim) addr=2dh; reset value=00h d4..0 = 0: programmed value is 53 d4..0 = 1: programmed value is 2 the step is 1.6 ma this register allows to program a line current limitation from 2 to 53ma with a step equal to 1.6ma. these values can be obtained using an external 15kohm resistor in kit with stlc3080. 5.20 slic off-hook threshold register (ith) addr=2eh; reset value=00h d3..0 = 0: programmed value is 16 ma d3..0 = 1: programmed value is 1 ma the step is equal to 1 ma. en = 1 the dc slic programmability block is enabled (ith and ilim) en = 0 the dc slic programmability block is disabled (ith and ilim) this register allows to program a threshold value from 1 to 16 ma with a step equal to 1ma. these values can be obtained using an external 12.5kohm resistor in kit with stlc3080. 5.21 pcm shift register (pcmsh) addr=50h; reset value=00h xs2..0:effective start of the tx frame is the programmed values of clock pulses (0 to 7) after the fs rising edge. rs2..0:effective start of the rx frame is the programmed values of clock pulses (0 to 7) after the fs rising edge. 5.22 pcm command register (pcmcom) addr=51h; reset value=00h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0101101 0 0 0 d4 d3 d2 d1 d0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0101110 0 0 0 en d3 d2 d1 d0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010000 xs2 xs1 xs0 rs2 rs1 rs0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010001 rr wr pc1 pc0 te rpab tpb tpa
23/46 STLC5048 tpa/b = these two bits are used to enable the dx outputs of the port a or/and b. according to the combination of these two bits the enabled port will be as follows: rpab = 0: port a enabled (dra input selected) rpab = 1: port b enabled (drb input selected) te = 0: transmit pcm data change on rising edge of mclk te = 1: transmit pcm data change on falling edge of mclk pc1-pc0 = selection of the channel for the pcm access data via mcu. wr = 1: setting this bit , receive pcm data writing via mcu (after a/ decoding) is enabled on selected channel and ipcm interrupt is generated every time fs signal becomes active, together to the set of the wrd bit in the pcmctrl register. a data byte must be written every 125 s, if data is not replaced the old value is inserted again but the pmw bit is set to 1 in the pcmctrl register. rr = 1: setting this bit, transmit pcm data reading (after a/ encoding) via mcu is enabled on selected channel and ipcm interrupt is generated every time that data are available, together to the se t of the rrd bit in the pc- mctrl register. a data byte must be read every 125 s, if data is not read the new value is written in the pcm access register but the pow bit is set to 1 in the pcmctrl register. 5.23 transmit time slot ch #0 (dxts0) addr=52h; reset value=00h en0=0:selected transmit time slot on dx output is in h.i. en0=1:selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi0. t06..0:define time slot number (0 to 127) on which pcm encoded signal of vfxi0 is carried out. if linear mode is selected (lin=1 of conf register) the 16 bits will be carried out as follows: the 8 most signifi- cant bits in the programmed time slot, the 8 least significant bits in the following time slot. example: if t06..t00=00: tpb tpa description 0 0 both ports disabled 0 1 port a enabled 1 0 port b enabled 1 1 both ports enabled pc0 pc1 description 0 0 channel #0 selected 1 0 channel #1 selected 0 1 channel #2 selected 1 1 channel #3 selected bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010010 en0 t06 t05 t04 t03 t02 t01 t00 ts0 ts1 1514131211109876543210
STLC5048 24/46 5.24 transmit time slot ch #1 (dxts1) addr=53h; reset value=00h en1=0: selected transmit time slot on dx output is in h.i. en1=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi1. t16..0: define time slot number (0 to 127) on which pcm encoded signal of vfxi1 is carried out. if linear mode is selected (lin=1 of conf register) the 16 bits will be carried out as follows: the 8 most signifi- cant bits in the programmed time slot, the 8 least significant bits in the following time slot. example: if t16..t10=00: 5.25 transmit time slot ch #2 (dxts2) addr=54h; reset value=00h en2=0: selected transmit time slot on dx output is in h.i. en2=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi2. t26..0: define time slot number (0 to 127) on which pcm encoded signal of vfxi2 is carried out. if linear mode is selected (lin=1 of conf register) the 16 bits will be carried out as follows: the 8 most signifi- cant bits in the programmed time slot, the 8 least significant bits in the following time slot. example: if t26..t20=00: 5.26 transmit time slot ch #3 (dxts3) addr=55h; reset value=00h en3=0: selected transmit time slot on dx output is in h.i. en3=1: selected transmit time slot on dx output is active carrying out the pcm encoded signal of vfxi3. t36..0: define time slot number (0 to 127) on which pcm encoded signal of vfxi3 is carried out. if linear mode is selected (lin=1 of conf register) the 16 bits will be carried out as follows: the 8 most signifi- cant bits in the programmed time slot, the 8 least significant bits in the following timeslot. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010011 en1 t16 t15 t14 t13 t12 t11 t10 ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010100 en2 t26 t25 t24 t23 t22 t21 t20 ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010101 en3 t36 t35 t34 t33 t32 t31 t30
25/46 STLC5048 example: if t36..t30=00: 5.27 receive time slot ch #0 (drts0) addr=56h; reset value=00h en0=0: disable reception of selected time slot. en0=1: selected receive time slot on dr input is pcm decoded and transferred to vfro0 output. r06..0: define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and transferred to vfro0 output. if linear mode is selected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. example: if r06..r00=00: 5.28 receive time slot ch #1 (drts1) addr=57h; reset value=00h en1=0: disable reception of selected time slot. en1=1: selected receive time slot on dr input is pcm decoded and transferred to vfro1 output. r16..0: define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and transferred to vfro1 output. if linear mode is selected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. example: if r16..r10=00: 5.29 receive time slot ch #2 (drts2) addr=58h; reset value=00h ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1010110 en0 r06 r05 r04 r03 r02 r01 r00 ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w101011 1 en1 r16 r15 r14 r13 r12 r11 r10 ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w101100 0 en2 r26 r25 r24 r23 r22 r21 r20
STLC5048 26/46 en2=0: disable reception of selected time slot. en2=1: selected receive time slot on dr input is pcm decoded and transferred to vfro2 output. r26..0: define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and transferred to vfro2 output. if linear mode is selected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. example: if r26..r20=00: 5.30 receive time slot ch #3 (drts3) addr=59h; reset value=00h en3=0: disable reception of selected time slot. en3=1: selected receive time slot on dr input is pcm decoded and transferred to vfro3 output. r36..0: define receive time slot number (0 to 127) on carrying the pcm signal to be decoded and transferred to vfro3 output. if linear mode is selected (lin=1 of conf register) the 16 bits will be used as linear code as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following timeslot. example: if r36..r30=00: 5.31 pcmw data register (pcmwd) addr=5ah; reset value=00h addr=5bh; reset value=00h this register is used to write receive pcm data via the mcu interface. writing this register the ipcm interrupt (if generated only by writing access) is automatically cleared. in a/ law only the first 8 bit are used. in linear code option both registers must be used. ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1011001 en3 r36 r35 r34 r33 r32 r31 r30 ts0 ts1 1514131211109865437210 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1011010 d7 d6 d5 d4 d3 d2 d1 d0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1011011 d15 d14 d13 d12 d11 d10 d9 d8
27/46 STLC5048 5.32 pcmr data register (pcmrd) addr=5ch; reset value=00h addr=5dh; reset value=00h read only this register is used to read transmit pcm data via the mcu interface. reading this register the ipcm interrupt (if generated only by reading access) is automatically cleared. in a/ law only the first 8 bit are used. in linear code option both registers must be read, first the lsb and after the msb. 5.33 pcm control register (pcmctrl) addr= 5eh; reset value=00h read only pmw = 1: data is not written every fs while writing pcm access data is enabled. pow = 1: data is not read every fs while reading pcm access data is enabled. wrd = 1: device is waiting for pcm data insertion in pcmwd register. the bit is reset after writing at least one byte. rrd = 1: data are available on pcmrd register. the bit is reset after reading the two bytes of the register (first the lsb and after the msb). 5.34 tone generation register (toneg) addr=60h; reset value=00h tn 0 =0,tn 1 =0: no tone is generated on ch #n tn 0 =1,tn 1 =0: a tone with 25hz frequency is generated on ch #n. tn 0 =0,tn 1 =1: a tone with 1khz frequency is generated on ch #n. tn 0 =1,tn 1 =1: a tone with 3khz frequency is generated on ch #n. this register allows the generation of a tone in the rx direction. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11011100 d7 d6 d5 d4 d3 d2 d1 d0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11011101 d15 d14 d133 d12 d11 d10 d9 d8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11011110 rrd wrd pow pmw bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1100000 t3 1 t3 0 t2 1 t2 0 t1 1 t1 0 t0 1 t0 0
STLC5048 28/46 5.35 coefficient state register (coefst) addr= 61h; reset value=f0h fr0..3=1: all channel filters and gain blocks are configured as defined in the ringing state fr0..3=0: all channel filters and gain blocks are configured as defined with the programmed value if also the corresponding fd bit is set to 0 fd0..3=1: all channel filters and gain blocks are configured as defined in the default state if also the correspond- ing fr bit is set to 0 fd0..3=0: all channel filters and gain blocks are configured as defined with the programmed value if also the corresponding fr bit is set to 0 5.36 software revision id code (swrid) addr=70h; read only. this register contains the dsp software revision code identifier. 5.37 hardware revision id code (hwrid) addr=71h; read only. this register contains the silicon revision code identifier. 6 single byte instruction 6.1 realignment command (reacom) this single instruction is used to realign the mcu interface in case of out of synchronisation. this instruction must be executed nmax+1 times to be successfull. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1100001 fd3 fd2 fd1 fd0 fr3 fr2 fr1 fr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11110000 00010100 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 11110001 00000001 name description id reacom realignment command 28h ckstart start checksum 29h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00101000
29/46 STLC5048 6.2 start checksum calculation (ckstart) this single instruction is used to start the checksum calculation of the enetered data used to configure the device. 7 command list (*) for this two commands the bit set in the comen register are not considered. 8 command description each command is transferred on every channel that has the proper bit in the comen register set to 1. 8.1 block enable command (blken) reset value=00h the command is used to enable/disable the b, z, r and x blocks be=1: the b block is equal to an open circuit be=0: the b block is configured as defined in the ringing state or with the programmed value ze=1: the z block is equal to an open circuit ze=0: the z block is configured as defined in the ringing state or with the programmed value re=1: the r block is equal to a short circuit re=0: the r block is configured as defined in the ringing state or with the programmed value xe=1: the x block is equal to a short circuit xe=0: the x block is configured as defined in the ringing state or with the programmed value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00101001 name description id blken block enable 22h kdf kd filter 30h afecff afe ka coefficient (*) 31h t_out timeout value (*) 32h grx receive gain 40h gtx transmit gain 41h rfc r filter coefficient 42h xfc x filter coefficient 43h bfc b filter coefficient 44h zfc z filter coefficient 45h bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0100010 xe re ze be
STLC5048 30/46 8.2 kd filter (kdf) the register is used to set the 3 coefficients (each of 16 bits) of the kd filter of the channel #n. 8.3 afe coefficient (afe_cff) reset value = aa00h kan0, kan1 = ka coefficient for ch #n according to the value of each couple of bits, the ka block is set in the following condition: kan1 kan0 0 x ka block disabled 1 0 ka set for low gain 1 1 ka set for high gain when the application involves also the metering pulse signal the afe of the STLC5048 must be adapted in or- der to manage also this signal. for this purpose is provided the ttx bit. ttx = 0: the current application is not using the metering pulse signal ttx = 1: the current application is using the metering pulse signal 8.4 timeout value (t_out) reset value=ffffh reset value = maximum value = ffffh (2048 us) to disable this function the t0 bit must be set to 0. to enable this function the t0 bit must be set to 1; the time-out value is set by means of t<15..1> bits. time_out = (t_out[15:1]*62.5 + 31.24)ns the minimum step is 62.5 ns. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0110000 . . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0110001 ka31 ka30 ka21 ka20 ka11 ka10 ka01 ka00 ttx bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w0110010 t7 t6 t5 t4 t3 t2 t1 t0 t15 t14 t13 t12 t11 t10 t9 t8
31/46 STLC5048 8.5 receive gain (grx) 00h: stop any received signal to reach the vfro0 analog output. in order to open the impedance synthesis feedback it?s necessary to mute the rx analog amplifier, as well. >00h: digital gain is inserted in the rx path equal to: 20log[prog.value/32768] the prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7fffh. 8.6 transmit gain (gtx) 00h: stop any transmit signal, null level is transmitted in the corresponding timeslot on dx output. >00h: digital gain is inserted in the tx path equal to: 20log[prog.value/32768] the prog. value must be espressed in 16 bits signed format: maximum prog. value is equal to 7fffh. 8.7 r filter coefficient (rfc) the register is used to set the 17 coefficients (each of 16 bits) of the r filter of the channel #n. 8.8 x filter coefficient (xfc) the register is used to set the 17 coefficients (each of 16 bits) of the x filter of the channel #n. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000010 . . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000011 . .
STLC5048 32/46 8.9 b filter coefficient (bfc) the register is used to set the 26 coefficients (each of 16 bits) of the b filter of the channel #n. 8.10 z filter coefficient (zfc) the register is used to set the 5 coefficients (each of 16 bits) of the z filter of the channel #n. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000100 . . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w1000101 . .
33/46 STLC5048 9 electrical characteristcs typical value are for 25c and nominal supply voltage. minimum and maximum values are guaranteed over the temperature 0-70c range by production testing and supply voltage range shown in the operating ranges. per- formances over -40 +85c range are guaranteed by product characterisation unless otherwise specified. symbol parameter test condition min. typ. max. unit digital interface vil input voltage low di pins 0 0.2vdd v vih input voltage high di pins 0.8vdd 5.5 v iil input current low di pins -10 10 a iih input current high di pins -10 10 a ci input capacitance (all dig. inp.) 5 pf vol output voltage low dx, tsx pins iol=3.2ma (other pins iol=1ma) 0 0.4 v voh output voltage high dx pin ioh=-3.2ma (other pins iol=1ma) 0.85vdd vdd v note: all digital input are 5v tolerant. analog interface rix transmit input amplifier input impedance (vfxi) 1m ? ror receive output impedance 1 ? power dissipation idd(pd) power down current 10 15 ma idd(act) active current 55 70 ma pcm interface timing f(mclk) master clock frequency 1.536 1.544 2.048 4.096 8.192 mhz twmh period of mclk high 38 ns twml period of mclk low 38 ns trm mclk rise time 10 ns tfm mclk fall time 10 ns thbf hold time mclk low to fsx/r high or low 10 ns tsfb setup time fsx/r high to mclk low 10 ns tdmd delay time, mclk high to data valid 15 ns tdmz delay time from mclk(8) low to data output disabled 15 40 ns tdfd delay time, fsx high to data valid if fsx rises later than mclk rising edge 15 ns tdmt delay time, from mclk and fsx both high to tsx low 20 ns tzmt delay time from mclk(8) low to tsx disabled 15 40 ns tsdm setup time, dr valid to mclk low 5ns thdm hold time, mclk low to dr invalid 5ns
STLC5048 34/46 figure 7. serial control port timing symbol parameter test condition min. typ. max. unit fcclk frequency of cclk 8mhz twch period of cclk high measured from vih to vih 40 ns twcl period of cclk low measured from vil to vil 40 ns trc rise time of cclk measured from vil to vih 20 ns tfc fall time of cclk measured from vih to vil 20 ns thcs hold time, cclk low to cs low 10 ns thsc hold time, cclk low to cs high 10 ns tssc setup time, cs transition to cclk low 10 ns tdsd delay time, cs low to co data valid 20 ns tcso cs off time 5 us tsdc setup time, ci. data in to cclk low 10 ns thcd hold time, cclk low to ci invalid 10 ns tdcd delay time, cclk low to co data out valid 30 ns tddz delay time, cs or cclk9 high to co high impedance pull up resistor = 1kohm cload = 30pf 30 ns mclk fsx dx tsx dr d94tl157 t hbf 123 45678910 t rm t fm t wmh t wml 1 2 3 4 5 6 70 t hbf 1 2 3 4 5 6 70 fsr t sdm t hdm t sfb t hbf t sfb t hbf t dmd t dfd t dmt t dmt t zmt t zmt 9 electrical characteristcs (continued)
35/46 STLC5048 9 electrical characteristcs (continued) figure 8. figure 9. slic control port timing slic control interface timing (dynamic configuration) symbol parameter test condition min. typ. max. unit tcs chip select repetition rate 31.25 s tcsw chip select pulse width 3.9 s tdcsl data out valid to cs low 1.95 ns tscsh data out held after cs high 1.95 ns tscsh set up time data in to cs high 50 ns thcsh hold time data in to cs high 10 ns cclk cs ci co d00tl471 123 45678 t rc t fc t wch t wcl 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 t dsd t dcd t hcs t sdc t hcd t ssc t scs t hsc t cso t doa t don 31.25 s (32khz) t div cs1 cs2 cs3 cs4 io (out) io (in) out ch0 in ch0 out ch1 in ch1 out ch2 in ch2 out ch3 in ch3 out ch0 d99tl460 in ch0 out ch1 in ch1 t dii
STLC5048 36/46 9 electrical characteristcs (continued) transmit transfer characteristics (all tests are performed in absolute gain condition (txg = gtxn = 0db) unless otherwise specified). symbol parameter test condition min. typ. max. unit absolute level at 0 dbm0 are: txg = 0db, gtxn = 0db 60 mvrms gxa transmit gain absolute accuracy -0.15 0.15 db gxag transmit gain variation with programmed gain (within 3 db from max dig. level) -0.2 0.2 db gfx gain variation with frequency (relative to gain at 1004hz); 0dbm0 input signal 50 hz 60hz 200hz 300-3000hz 3400hz 4000hz 4600hz and above -1.8 -0.15 -0.7 -20 -20 0 0.15 0 -14.0 -32.0 db gaxt gain variation with temperature -0.10 0.10 db gaxe gain variation with supplies +/- 5% 0dbm0 input signal -0.05 0.05 db gtx gain tracking with tone (1004hz mu law, 820hz a law) (1) (1) vfxi=106mvrms, txg=+3.52db, gtx=-8.308db (levels and gain condition eqivalent to 0dbr with zadm = 600 ohm on the applicatio n) gsx = 3 to -40dbm0 gsx = -40 to -50dbm0 gsx = -50 to -55dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db qdx quantization distortion with tone (1004hz mu law, 820hz alaw) vfxi = +3dbm0 vfxi = 0 to -30dbm0 vfxi = -40 dbm0 vfxi = -50 to -55 dbm0 33 36 30 15 db nct transmit noise c message weighted (mu and a law) 12 dbrnco npt transmit noise psophometric weighted @ 0dbr, zadm=600ohm (2) (2) txg=+3.52db, gtx=-8.308db (gain condition eqivalent to 0dbr with zadm = 600 ohm on the application) (3) the max value includes 125 sec for the time slot synchronization. -68 dbm0p dax absolute delay (3) b = 0, z = 0, x = r = 1 462 587 s dpxm single frequency distortion (mu law 0dbm0 sinewave @ 1004hz) -46 db dpxa single frequency distortion (a law 0dbm0 sinewave @ 820hz) -46 db gspx out of band spurious noise 61mvrms at vfxi 4200hz to 72khz -39 dbm0
37/46 STLC5048 9 electrical characteristcs (continued) (1) values related to the application including the external filter on rx. the maesure is referred to the signal replicas. (2) the max value includes 125 sec for the time slot synchronization. receive transfer characteristics (all tests are performed in absolute gain condition (rxg = grxn = 0db) unless otherwise specified). symbol parameter test condition min. typ. max. unit absolute levels at 0 dbm0 are: rxg = 0db, grxn = 0db 547 mvrms gra transmit gain absolute accuracy -0.15 0.15 db grag receive gain variation with programmed gain (within 3 db from max dig. level) -0.2 0.2 db gfr gain variation with frequency (relative to gain at 1004hz); 0dbm0 input signal below 200hz 200hz 300-3000hz 3400hz 4000hz -0.25 -0.15 -0.7 0.115 0.15 0.15 0 -14 db gart gain variation with temperature 0 to 70 c -0.10 0.10 db gare gain variation with vcc=vdd= 3.3v +/- 5% 0dbm0 input signal -0.05 0.05 db gtr gain tracking with tone (1004hz mu law, 820hz alaw) dr = 3 to -40dbm0 dr = -40 to -50dbm0 dr = -50 to -55dbm0 -0.2 -0.4 -1.2 0.2 0.4 1.2 db qdr quantization distortion with tone (1004hz mu law, 820hz alaw) dr = 3 dbm0 dr = 0 to -30dbm0 dr = -40 dbm0 dr = -50 to -55dbm0 33 36 30 15 db ncr receive noise c message weighted (mu law) 811 dbrnco npr receive noise psophometric weighted (a law) -79 dbm0p dar absolute delay (2) b = z = 0, x = r = 1 325 450 s dpr1 single frequency distortion (0dbm0 sinewave @ 1004hz) -46 db gspr out of band spourious noise 0dbm0 dtmf tone at dr -60 db 0dbm0 180 to 3600hz sinewave at dr -43 db obn out of band noise (1) integral measure from 3.4 to 128khz g tx = g rx = 0db g tx = 0db; g rx = -7db -48 -51 dbm dbm spectral measure from 3.4 to 200khz in b/w = 30hz -70 dbm
STLC5048 38/46 figure 10. group delay distortion mask supply rejection and crosstalk symbol parameter test condition min. typ. max. unit psrr power supply rejection ratio 1khz, 50mvrms 0 to 70c 42 65 db ctx-r transmit to receive crosstalk (input signal 200hz to 3450hz at 0dbm0) -76 db ctr-x receive to transmit crosstalk (input signal 200hz to 3450hz at 0dbm0) -76 db ct-ich inter channel crosstalk, tx and rx direction. input 200 to 3450 hz at 0dbm0 at vfxi of one channel; all other vfxi inputs and all dr inputs receive idle signal. output is measured at dx of the 3 idle channels. input of 200 to 3450 hz at 0dbm0 pcm at dr on ione channel. all other dr inputs and all vfxi inputs receive idle signal. output is measured at vfro of the 3 idle channels -78 db d02tl523 rx 500 1000 1500 2500 3000 f(hz) 0 100 200 300 400 500 600 delay ( s) 2000 tx d02tl524 500 1000 1500 2500 3000 f(hz) 0 100 200 300 400 500 600 delay ( s) 2000 rx direction tx direction 9 electrical characteristcs (continued)
39/46 STLC5048 10 appendix a 10.1 STLC5048 absolute gains in kit with l3235n/stlc3080 figure 11. STLC5048 in kit with stlc3080 ac application diagram. figure 12. STLC5048 in kit with l3235n ac application diagram. in fig.11 is shown the application diagram of the STLC5048 in kit with the stlc3080 slic. the figure is related to the ac path as the STLC5048 doesn't perform any dc processing. the only dc feature performed by STLC5048 is the off-hook and limitation threshold programmability. the same application diagram for the ac processing can be applied to the kit with the l3235n (as shown in fig. 12): the only differences are the following: the scaling factor of the iline is 50 rs value is 4.1 kohm. the impedance synthesis is fully performed by STLC5048; the l3235n slic (or the stlc3080) used in kit with the STLC5048 just splits the ac/dc component of iline, scales it and traduces it into a voltage via rs. as shown in fig. 12, the scaled current is converted into a voltage through the external resistor rs = 4100 ohm (8200 ohm for the stlc3080): this value is fixed (i.e. independent on the administration): the attenuation be- tween vline and vfxi is dependent on the administration. considering the tx gain we can proceed as follows for the gain calculation: txg = 0db grx tip rs cac iltf rdc d00tl472 iline/100 r s 8200 ? ring r p r p vfro vfxi gtx channel filter eco canceling z synthesis channel filter + + rx dr dx 2 -1 1 zadm iline tx 1 STLC5048 grx tip rpc cac il d00tl473 iline/50 r s 4100 ? ring r p r p vfro vfxi gtx channel filter eco canceling z synthesis channel filter + + rx dr dx 2 -1 1 zadm iline tx 1 STLC5048
STLC5048 40/46 gx = 0db (as reported in the absolute gain levels with 61vrms at vfxi and gx=0db, the dx output is 0dbm0). for instance let's calculate which tx gain to program if +4.2dbr @ 600 ohm is to be set: vline = 0dbm @ 600ohm in case of stlc3080 the scaling factor is 100 (instead of 50) while the rs value is 8200 (instead of 4100) so the result is the same. refering to the formula (1), to have dx equal to 4.2db with vline=0dbm gx must be set to gx = 4.2 - 4.78 = -0.58db. figure 13. absolute gain in tx path. vfxi vline 600 ------------------ - 1 50 ------ 4100 ?? = v fxi vline 600 ------------------ - 1 100 --------- - 8200 ?? = vline d00tl474 iline r s 4100 ? (8200 for stlc3080) vfxi vfxi = (-iline/50)*4100 for l3235n vfxi = (-iline/100)*8200 for stlc3080 gx txg 1/100 for stlc3080 1/50 dx zadm STLC5048 l3235n
41/46 STLC5048 11 appendix b 11.1 STLC5048 application diagrams figure 14. STLC5048 plus l3235n/l324 kit application diagram zac za zb zs=4100 ? 2.2k ? 150 ? 43 11 10 9 rx cac il cac 100 f 6 18 28 32 gdk 31 oh 25 rng 27 sby 3 bgnd 13 v cc cvss cvb cvcc v ss agnd v bat v ss v cc v bat 17 2 39 29 cs vreg base ring 38 40 ? tip 40 40 ? v bat tip r p1 r p1 ring r p2 20 ? r p2 20 ? 44 22 20 24 14 35 vpol lim ref gkf rf 39k cf 390nf cr 4.7 f rlim 9.1k to 35k rr 51k rgf 39k d98tl381c l3235n text mje350 overvoltage protection 82 ? 10 f d1 1n4007 rt 1m ? 82 ? 10 f d2 1n4007 34 rtf cgf 390nf 0.1 f 0.1 f 0.1 f puneg tx 12 7 cs 4.7 f vring STLC5048 io0 io1 io2 io3 io4 io11 io12(cs0) io13(cs1) io14(cs2) io15(cs3) 0.1 f gnd v cc v cc dx dr fs mclk tsx int res cs cclk co ci vfxi0 1m serial control ports vfro0 100nf ctx 100nf gnd va 0.1 f 0.1 f v100 v cc gnd 63 1 5 4 7 2 l3234 v cc v ee v dd v dd v ss sub vfro1 vfro2 vfro3 vfxi1 vfxi2 vfxi3 0.1 f 10nf 10nf 6.8m
STLC5048 42/46 figure 15. STLC5048 plus stlc3080 application diagram. zac rs zb mode rs 20 19 41 17 rx iltf rdc cac cac 26 25 14 12 61 60 59 58 57 28 33 35 19 20 21 22 23 24 62 29 53 53 39 38 42 43 48 46 24 49 34 47 4 5 d2 43 det 44 gdk/al 3 d0 6 7 1 2 r0 r1 csin csout vreg base vbat ring rt1 39 r p1 r s1 r s2 tip pcd 38 40 rdc v bat v bat v bat tip vrel rr vring r p1 rt ring r p2 r p2 36 35 16 27 34 rt2 d99tl459d stlc3080 qext lcp 1511 28 crt d1 8 30 42 11 res ttxin ttx ith ith ckring crt rda rth rttx cttx rlim 23 tx 22 8 9 41 10 11 14 13 12 27 54 3 4 7 5 6 21 zac1 STLC5048 io0 io1 io2 io3 io4 io5 io6 io7 io8 cs1 cs2 io9 io10 io11 cs0 cs3 0.1 f gnd v cc v cc (3.3v) dxa pcm interface dra 16 15 dxb drb fs mclk tsx m1 cap cap 0.1 f m0 int cs cclk co 40 ci vfxi0 serial control ports to other slics components needed only for metering pulse injection vfro0 ctx 100nf to other slics to other slics v dd (3.3v) v cc (5v) bgnd rel0 rel1 relr v dd v cc agnd v cc v ee v dd v dd v ss sub vfro1 vfro2 vfro3 vfxi1 vfxi2 vfxi3 0.1 f 31 rlim ilim ref 32 iref vbg 13 37 29 10 9 crev crev csrv bgnd and agnd must be shorthed together on the line card cvb csrv 33 18 2.2k ? 150 ? 1m 10nf 100nf 10nf 6.8m
43/46 STLC5048 12 appendix c 12.1 power up sequence the dsp after an hw (m1=0) or sw reset (conf[7]=1) or a power-on reset (por) has to perform the init program. to do it at least one channel must be set in active mode. after that, (2 fs are required), the init bit in the ctrlack register is set to 1 and the ram can be written and read. it must be noted that to program the device the mclk and fs signals must be applied to the device. following, the correct sequence that must be used in order to program the device. 12.2 power on sequence wait 5 fs signals for pll locking conf=bf sw reset enabled after reset write conf=3f sw reset disabled write conf=30 all channel active wait 2 fs signals read ctrlack=03 check init bit =1 before to start the coefficent download, one or more channels must be selected using the comen register. the download can be done keeping the device in active mode (at least one channel active) or in power down mode (all channels in power down). if the second choice is selected, the pdr bit in the comen register must be set to 0 (internal ram active also in power down mode).
STLC5048 44/46 13 package information figure 16. tqfp64 mechanical data & package dimensions outline and mechanical data a a2 a1 b c 16 17 32 33 48 49 64 e3 d3 e1 e d1 d e 1 k b tqfp64 l l1 seating plane 0.08mm dim. mm inch min. typ. max. min. typ. max. a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.0066 0.0086 0.0106 c 0.09 0.0035 d 11.80 12.00 12.20 0.464 0.472 0.480 d1 9.80 10.00 10.20 0.386 0.394 0.401 d3 7.50 0.295 e 0.50 0.0197 e 11.80 12.00 12.20 0.464 0.472 0.480 e1 9.80 10.00 10.20 0.386 0.394 0.401 e3 7.50 0.295 l 0.45 0.60 0.75 0.0177 0.0236 0.0295 l1 1.00 0.0393 k 0? (min.), 3.5? (min.), 7?(max.) ccc 0.080 0.0031 tqfp64 (10 x 10 x 1.4mm) 0051434 e ccc
45/46 STLC5048 14 revision history table 7. revision history date revision description of changes january 2003 7 first issue in edocs dms/ april 2005 8 changed figures 13 & 14: figure 13 added a resistance 6.8m ? between pin vfxi0-STLC5048 and pin tx-l3235n; figure 14 added a resistance 6.8m ? between pin vfxi0-STLC5048 and pin tx-stlc3080.
46/46 STLC5048 esd - the stmicroelectronics internal quality standards set a target of 2 kv that each pin of the device should withstand in a series of tests based on the human body model (mil-std 883 method 3015): with c = 100pf; r = 1500w and performing 3 pulses for each pin versus vcc and gnd. device characterization showed that, in front of the stmicroelectronics internaly quality standards, pin 25 of STLC5048 withsta nd at least 1000v. the above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in t he field. nonetheless they must be mentionned in connection with the applicability of the different sure 6 requirements to STLC5048. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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